---

Abstract

Assuring the correctness of computing systems is fundamental to our society and economy, and formal verification is a class of techniques approaching this issue with mathematical rigor. Researchers have invented numerous algorithms to automatically prove whether a computational model, e.g., a software program or a hardware digital circuit, satisfies its specification. In the past two decades, Craig interpolation has been widely used in both hardware and software verification. Despite the similarities in the theoretical foundation between hardware and software verification, previous works usually evaluate interpolation-based algorithms on only one type of verification tasks (e.g., either circuits or programs), so the conclusions of these studies do not necessarily transfer to different types of verification tasks. To investigate the transferability of research conclusions from hardware to software, we adopt two performant approaches of interpolation-based hardware model checking, (1) Interpolation-Sequence-Based Model Checking (Vizel and Grumberg, 2009) and (2) Intertwined Forward-Backward Reachability Analysis Using Interpolants (Vizel, Grumberg, and Shoham, 2013), for software verification. We implement the algorithms proposed by the two publications in the software verifier CPAchecker because it has a software-verification adoption of the first interpolation-based algorithm for hardware model checking from 2003, which the two publications use as a comparison baseline. To assess whether the claims in the two publications transfer to software verification, we conduct an extensive experiment on the largest publicly available suite of safety-verification tasks for the programming language C. Our experimental results show that the important characteristics of the two approaches for hardware model checking are transferable to software verification, and that the cross-disciplinary algorithm adoption is beneficial, as the approaches adopted from hardware model checking were able to tackle tasks unsolvable by existing methods. This work consolidates the knowledge in hardware and software verification and provides open-source implementations to improve the understanding of the compared interpolation-based algorithms.

Reproduction Information

A reproduction package of this work is available on Zenodo (). It was reviewed by the Artifact Evaluation Committee at FSE 2024 and awarded the (Functional and) Reusable and Available badges. Notably, it won the ACM SIGSOFT Best Artifact Award. The SVN repository (corresponding git commit) contains the revision of CPAchecker used in the evaluation.

 

---

 

Experimental Results

The experimental results reported in the paper can be viewed in the interactive tables linked below. You can click on the cells in the status columns to see the respective log output and navigate through the tabs to view various plots.

• Table 1 (summary of the experimental results)
• Table 2 (left) (H1.C)
• Table 2 (right) (H2.E)
• Figure 1a (H1.A)
• Figure 1b (H1.B)
• Figure 2a (H1.C and H2.E)
• Figure 2b (H1.C and H2.E)
• Figure 3a (H2.E)
• Figure 3b (H2.B)
• Figure 4a (H2.C)
• Figure 4b (IMC) (H2.D)
• Figure 4b (DAR) (H2.D)